To add bit-shifting capability to the SAP-1, the first step is to replace one of the registers with a shift register. In this case, the Accumulator makes the most sense to replace. The 74HC194 has an almost identical logical layout to the 74HC173 so it makes an ideal part to use.
The SL and SR pins are the serial input left and serial input right pins, respectively. SR of U25 connects to the most significant bit of the lower nibble. SL of U24 connects to the least significant bit of the upper nibble. Thus when a left shift occurs, the highest bit of the lower nibble becomes the lowest bit of the upper nibble. When a right shift occurs, the lowest bit of the upper nibble becomes the highest bit of the lower nibble.
The new parts require an additional control signal. Since all the outputs of the microcode ROMs are used, an additional ROM needs to be added (A decoder + 2 ROMs can be used, but this requires a complete re-write of the microcode). The address inputs are identical to the other ROMs. However, there are now up to 8 additional control signals available for use. The simplify the updating of the circuit, the old /La load accumulator signal will remain unused. Two new signals, Asl and Asr are added and connect to the mode select inputs of the 74HC194.
The microcode must now be updated to work with the new control word. When Asl and Asr = 0 then the currently stored bits are not changed. When Asl and Asr = 1 then the bits on the parallel inputs are loaded in to the register on the rising edge of CLK. When Asl = 1 and Asr = 0 the bits are shifted left by one bit on the rising edge of CLK, the bit present at SL is shifted in to the lowest bit of the register. When Asr = 1 and Asl = 0 the bits are shifted right by one bit on the rising edge of CLK, the bit present at SR is shifted in to the highest bit of the register.
With the microcode ROM it is very simple to update the control signals to add new functions. Operations that previously used the /La signal are updated to use Asl/Asr. Two new OpCodes have been added: SL for shift left and SR for shift right.
To give an idea of how the control word data is organized in the ROMs, here is a memory map of some of the opcodes: (The full spreadsheet is available in the linked schematic file at the end.)
There are 3-bits for the T-state, so each OpCode can have up to 8 micro-instructions. The next highest 4 address lines connect to the instruction register. With 4 bits this means there can be up to 16 opcodes. So within the ROM each OpCode uses up a fixed set of 8-bytes. Because hexadecimal uses 4-bits for each number, the address for each OpCode will start on 0h or 8h. However the first 2 instructions are always the fetch cycle, so the unique micro-instructions for each OpCode will start on either 2h or Ah.