Friday, February 28, 2014

Modifying the SAP-1 Control Matrix

Extending the instruction set and capabilities of the SAP-1 using the original control matrix design allows you to avoid having to purchase an EEPROM/Flash programmer.  However adding more than a few new opcodes can quickly become very complicated.  As an example, the accumulator will be modified to support left and right shifting of the data.  This modification was described in the post SAP-1 with Shift Register and Microcoded ROM.  The design of the accumulator here is identical.

Two new instructions need to be added: SL (opcode 3h) for Shift Left and SR (opcode 4h) for Shift Right.  To execute these the control word needs to be modified.  The /La control signal is replaced with two signals, Asl and Asr, which connect to the mode select inputs of the shift registers.

To support the new instructions, two extra decoding gates have to be added to the instruction register.  Recall that the purpose of the instruction decoder is to convert the 4-bit opcode in to a single active signal.

For example, when the instruction register is loaded with ADD (opcode 0h) then only the LDA line is active, ADD, SUB, OUT, SL, SR and /HLT will be inactive.  To further simplify the circuit, this part of the controller sequencer can be replaced with a 3-bit to 1-of-8 line decoder such as the 74HC238.

The ring counter circuit remains unchanged.  Again, its output is such that only 1 of the 6 lines is active during a clock cycle.

Together these two groups of signals drive the control matrix, which outputs the control word: the collection of signals which activate the individual components of the computer.  A series of control words (micro-instructions) execute the function represented by the opcode.

Next, much like with the microcode ROM design, the microcode for each instruction is mapped out.  Once this is done the logical equation that describes each bit of the control word can be derived. 

Note: the Excel spreadsheet is found in the file linked at the end of this post.

From this table, a logic equation can be written for each control signal.  From this the configuration of the control matrix will be derived.  For example: Asl = (T4 & SL) + (T5 & LDA) + (T6 & ADD) + (T6 & SUB).  [Note: & is boolean AND, + is boolean OR]. Asl is active during T4 when the opcode is SL or during T5 when the opcode is LDA or during T6 when the opcode is ADD or during T6 when the opcode is SUB.  Check the spreadsheet for a breakdown of all the control signal decoding.

Some patterns should start to reveal themselves.  The T1, T2 and T3 states are always the same because they are part of the Fetch cycle.  Ep and /Lm are always active during T1, Cp is always active during T2 and /CE and /Li are always active during T3.

Now map out the equation in to the actual logic gates.  The original SAP-1 design mostly uses NAND gates in the control matrix.  Replacing the lower NAND with its DeMorgan equivalent reveals the true logic.  This circuit could be replaced with an equivalent configuration of AND and OR gates (or AND and NOR gates for active low output).

Each bit of the control word will need a similar set of gates.  A program such as Logic Friday can assist with converting the equations to logic gates. Here is another configuration of the Asl control line:

As another example, here is the /Lm control signal:

Link to a RAR file containing the schematic and full description of the control matrix.

Sunday, February 23, 2014

SAP-1 with Shift Register and Microcoded ROM

 To add bit-shifting capability to the SAP-1, the first step is to replace one of the registers with a shift register.  In this case, the Accumulator makes the most sense to replace.  The 74HC194 has an almost identical logical layout to the 74HC173 so it makes an ideal part to use.

The SL and SR pins are the serial input left and serial input right pins, respectively.  SR of U25 connects to the most significant bit of the lower nibble.  SL of U24 connects to the least significant bit of the upper nibble.  Thus when a left shift occurs, the highest bit of the lower nibble becomes the lowest bit of the upper nibble.  When a right shift occurs, the lowest bit of the upper nibble becomes the highest bit of the lower nibble.

The new parts require an additional control signal.  Since all the outputs of the microcode ROMs are used, an additional ROM needs to be added (A decoder + 2 ROMs can be used, but this requires a complete re-write of the microcode).  The address inputs are identical to the other ROMs.  However, there are now up to 8 additional control signals available for use.  The simplify the updating of the circuit, the old /La load accumulator signal will remain unused.  Two new signals, Asl and Asr are added and connect to the mode select inputs of the 74HC194.

The microcode must now be updated to work with the new control word.  When Asl and Asr = 0 then the currently stored bits are not changed.  When Asl and Asr = 1 then the bits on the parallel inputs are loaded in to the register on the rising edge of CLK.  When Asl = 1 and Asr = 0 the bits are shifted left by one bit on the rising edge of CLK, the bit present at SL is shifted in to the lowest bit of the register.  When Asr = 1 and Asl = 0 the bits are shifted right by one bit on the rising edge of CLK, the bit present at SR is shifted in to the highest bit of the register.

With the microcode ROM it is very simple to update the control signals to add new functions.  Operations that previously used the /La signal are updated to use Asl/Asr.  Two new OpCodes have been added: SL for shift left and SR for shift right.

To give an idea of how the control word data is organized in the ROMs, here is a memory map of some of the opcodes: (The full spreadsheet is available in the linked schematic file at the end.)

There are 3-bits for the T-state, so each OpCode can have up to 8 micro-instructions.  The next highest 4 address lines connect to the instruction register.  With 4 bits this means there can be up to 16 opcodes.  So within the ROM each OpCode uses up a fixed set of 8-bytes.  Because hexadecimal uses 4-bits for each number, the address for each OpCode will start on 0h or 8h.  However the first 2 instructions are always the fetch cycle, so the unique micro-instructions for each OpCode will start on either 2h or Ah.