SAP-1 Simple as Possible Computer with Discrete Component RAM

I have been asked a few times how to design a 16-byte RAM using standard TTL parts.  One way to do this is to use 8-bit registers to hold each byte.  A 74LS373 is an 8-bit latch type register with 3-state outputs, several chips can share the same input and output buses.  Two 74LS138 and two 74HCT238 3-bit to 8-line decoders are used for decoding the addresses.

Each decoder has two active low enable inputs and one active high enable input.  Internally they translate a 3-bit number to activate 1 out of 8 outputs.  The '138 has active low outputs, if the chip is not enabled then all outputs are high.  The '238 has active high outputs, if the chip is not enabled then all outputs are low.  The least significant 3 bits of the 4-bit address (from the MAR) connect to the select inputs.  The most significant bit connects to the (active low) enable of the first decoder and the (active high) enable of the second encoder.  So addresses 0 through 7 activate the lowest 8 lines and addresses 8 thought 15 activate the highest 8 lines.  Finally, either the WEram (write enable ram) or CE (chip enable) signals must go low for any of the control signals to activate.

These Input and Output signals go to each individual register chip.  To enter data, the address and data is set using the DIP switches (in Program mode) and the Write Memory button is pressed.  This sets the LE signal of the register high and the data is latched in to memory.  When reading data the controller/sequencer sends the CE signal to the memory decoder and whichever register is selected by the MAR outputs its data to the W-bus.

I have also made a second design that uses an additional 74LS245 bus transceiver.  This allows you, during simulation in ISIS, to view what data is actually stored in each byte of RAM.

Here is a file that contains the schematics for each design.

ASAP-2 Almost Simple As Possible Computer - Version 2

Here is version 2 of my ASAP-2 Almost Simple As Possible Computer.  A few changes have been made to the circuit.

The conditional jumps will have either 6 or 9 T-states depending on whether the condition is true.  During a jump operation the selector will choose among the flags depending on the opcode (Jump if Positive microcode shown).  If the condition is false and jump is enabled, the output of U9 will be high and the sequence will simply increment the program counter to the next opcode.  If the condition is true and jump is enabled then U9 will go low.  The controller sequencer will then load the value 8 (D3 = 1, D2,D1,D0 = 0) on the positive going clock edge and the micro-instruction pointer will now be at the 9th instruction; this will carry out loading the program counter with the new value.

The I/O Ports are addressable by an 8-bit number, so up to 256 of either inputs or outputs can be supported by the I/O opcodes.  In this case minimal decoding is used and only 2 inputs and 2 outputs are placed.  During an operation the port selector buffer is loaded with the chosen I/O number.  This is decoded to pass along the enable signal to the correct port.  When active, either a low buffer enable or a positive going clock will be passed to the selected port.  The inputs are simply an 8-line 3-state buffer.  The outputs are 8-bit D-Type registers.

Dealing with the Carry Flag becomes quite complicated since a number of different opcodes affect the Carry Flag.  When rotating or shifting the accumulator, the previous MSB/LSB becomes the Carry Flag; but depending on the operation, the old Carry Flag may or may not be shifted in as the new MSB/LSB.  Some ALU operations use the current value of the Carry Flag, others need either a 1 or a 0 to get the correct result.  The two data selectors route the Carry Flag and the MSB/LSB of the accumulator to support Rotate Left/Right, Rotate-Through Carry Left/Right and Arithmetic Shift Left/Right.

 

Link to a RAR file of the schematics, ROM files and microcode.

SAP-1 ISIS/Proteus Design Suite 7.0 Schematic Files

There have been some requests for the SAP-1 schematics that can be opened in older versions of ISIS/ Proteus Design Suite.  Here is a file containing all the schematics saved as ISIS 7.0 format.

ASAP-2 Almost Simple As Possible Computer 2

Here is what I call the ASAP-2 Almost Simple As Possible Computer.  It is based on the SAP-2 as described in Digital Computer Electronics by Albert Malvino.  I made a few changes to the design: there is only one input register, the memory is split in to a 32kB ROM and 32kB RAM, the ALU supports a Carry flag, the OPcodes no longer follow the 8085 numbering and I have more than doubled the number of OPcodes.

The basic architecture of the circuit:

Having the ALU A input directly connected to the W-bus adds a lot of flexibility to the design.  I originally had a temporary register on both ALU inputs but this required another 3-state buffer on the ALU output.

The schematic was made using Proteus Design Suite version 8.0 SP1 and the demo version should be able to view and simulate the circuit.

Link to a RAR file of the schematics, ROM files and microcode.

I consider this to be a work in progress.  I plan to add some more decoding on the controller/sequencer to get the number of ROMs down to 4 (ROMs $ > 74HC138 $).  It was probably a mistake to change the I/O functions to 1 byte commands as this limits the ability to address and expand the I/O bus.  Also, adding some OPCodes that use the B/C registers as a memory address pointer would be useful.

SAP-1 with a Microcoded ROM

Here is my attempt at designing a SAP-1 microprocessor with a micro-code ROM controller sequencer and a variable machine cycle.  The total number of ICs has decreased from 48 to 35.  My design deviates a bit from the block diagram shown at the end of chapter 10.  Looking at Digikey's catalogue, 16x4-bit or 16x8-bit ROMs are simply not available anymore.  I ended up using two 8Kx8-bit ROMs to give a 16-bit control word.  Obviously only a tiny fraction of the storage is used.  Also, the simulation program only has a few parallel access ROMs in its library anyway.  I took advantage of this wider address space to simplify the design.  Something like the AT28C64B (Digikey Part Page) can be used.  You will also need an EEPROM programmer; many inexpensive but adequate ones are available on eBay.

The OPCode half of the instruction register outputs directly to the address lines of the micro-code ROMs.  To simplify things, each instruction's microcode takes up a fixed block of 8-bytes, this allows for up to 8 micro-instructions for each routine.  Each instruction has 4-bits for the OPCode so there can be up to 16 OPCodes; this iteration of the SAP-1 has 8 instructions in its set.  Each machine cycle executes as follows:

• T1: Load the memory address register from the program counter.
• T2: Increment the program counter, load instruction from the RAM.
• As soon as the instruction is loaded from RAM, the ROM address now points to the microcode for that instruction.
• T3,T... Continue executing the instruction.
• NOP: This resets the Controller/Sequencer counter back to zero and the machine cycle repeats.

 To save on manually entering a program each time the simulation is run, I have added an auto-loader circuit that will load into RAM a program saved in a ROM.  In the simulation, the ROMs are loaded from a linked binary file, which can be edited with a Hex editor to change the program.  Three 2:1 data selectors (think of them as a gang operated 4PDT switch) were added to easily switch between run/execute, manual programming and auto-programming.  Unfortunately the data input circuit is now much more convoluted.

The contents of memory once the auto-loader has completed.

And here the contents of the accumulator has been transferred to RAM by the store instruction.

The ROM allows for much more flexibility in creating and editing the instruction set.  The Jump, Store and Output memory instructions have been added to the original set.



The microcode for each instruction.  Thank-you to Kyle at 8-bit Spaghetti where I first saw this nice layout for the microcode.  He also has a build log of his own SAP-1 computer.

Link to a RAR file the of schematics, ROM binaries and microcode. 

SAP-1 Updated Design

Here is the updated design for the SAP-1 microprocessor.  I've made a number of changes that should allow someone to build this circuit using parts that are readily available from a place like Digikey.  To summarize:

• All parts changed to 74HC high speed CMOS, no more worries about fanout limits and sinking vs. sourcing differences in current.  However the unused gates (not shown) will have to be properly terminated as per the usual issues with floating hi-impedance inputs.
• Some newer parts have been used (4-bit counter, octal 3-state buffer) to simplify the design and reduces the chip count.
• The 74LS189 RAM has been replaced with a 32kB CMOS Asynchronous Static RAM.  A part like the Cypress Semiconductor CY7C199CN can be used for the RAM (Digikey Part Page).
• Since the RAM uses the same pins for input and output, another set of 3-state buffers is used to output or isolate the data switches from the W-bus.
• To clean up the schematic the W-bus is only shown as a connection to a common bus.
• A logic analyzer has been added to show how the control signals are sequenced.

This design still utilizes a hardwired controller sequencer.  Any changes to the microcode require a complete re-design of this circuit which is very cumbersome.  The next design will utilize a microcoded ROM to handle the control sequence, as outlined at the end of the chapter.

Here is the memory contents of a sample program entered into the SAP-1.  It can be found on page 146 of Digital Computer Electronics (Example 10-3).

Link to schematic file.
Link to PDF of schematic.

SAP-1 Simple As Possible Computer

Here is an almost identical recreation of the SAP-1 Simple As Possible microprocessor, as published in Digital Computer Electronics by Albert Malvino and Jerald Brown.  While the book is out of print an "ebook" can be found fairly easily if you know where to look.

I used Labcenter Electronics' Proteus Design Suite to draw the schematic.  A demo version can be downloaded from http://www.labcenter.com/index.cfm under the download tab.  It can do everything except save or print, so the circuit can be simulated when opened (use the Import Legacy Design).

Unfortunately the original design uses 74LS189 16x4-bit RAM, which can only be found on eBay right now.  That means it would be difficult to actually build this circuit.  I am working on an updated design that uses 74HC chips and other commonly available parts.  For now you can try out the classic design and see how it works for yourself.

Link to Schematic File.
Link to PDF of Schematic.